Technical Field
The present invention relates to an electronic device and a method of manufacturing the same.
Related Art
As a known method of manufacturing an electronic device, for example, there is provided one which is disclosed in Japanese Laid-open patent publication No. 2003-309215. In a manufacturing method described in the same document, a multilayer interconnect layer is formed by laminating a plurality of interconnect layers on a supporting substrate, and then, the supporting substrate is removed. Then, a solder ball is formed as an external electrode terminal on one surface of the multilayer interconnect layer which is exposed by the removal of the supporting substrate. Furthermore, electronic components are mounted in a flip chip configuration on the other surface of the multilayer interconnect layer. This can obtain an electronic device on which electronic components are placed on the multilayer interconnect layer.
In addition, as conventional art documents related to the present invention, there may be included Japanese Laid-open patent publication Nos. 57-7147, 9-321408, 11-126978, 2001-53413 in addition to Japanese Laid-open patent publication No. 2003-309215.
By the way, in the above electronic device, in order to perform microscopic connection between the interconnect layer and the electronic component, resin suitable for micromachining is required to be used in an interconnect layer on the electronic component side in the interconnect layers which constitute the multilayer interconnect layer. On the other hand, there are many cases where the resin suitable for micromachining is not required to be used in an interconnect layer on the solder ball side. In this case, it is preferable to use resin with relatively low cost in the interconnect layer on the solder ball side to reduce costs of the electronic device.
However, in the manufacturing method disclosed in Japanese Laid-open patent publication No. 2003-309215, as described above, the multilayer interconnect layer is formed by laminating a plurality of interconnect layers in order on the supporting substrate. Therefore, the interconnect layer on the solder ball side is formed prior to forming the interconnect layer on the electronic component side. As a result, there is a restriction in that resin which is lower in decomposition temperature than the resin which constitutes the interconnect layer on the electronic component side cannot be used as the resin which constitutes the interconnect layer on the solder ball side. The resin for use in the interconnect layer on the solder ball side is limited for such a restriction, and accordingly, reduction in cost of the electronic device is hindered.